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| tps65200 slvsa48a ? april 2010 ? revised september 2015 tps65200 li+ battery charger with wled driver and current shunt monitor 1 features ? up to 90% efficiency ? current shunt monitor 1 ? battery switching charger, wled driver, and current shunt monitor in a single package ? fixed gain of 25 v/v ? battery charger ? input referred offset voltage less than 40 v typical enables use of shunt ? charges faster than linear chargers resistors as low as 20 m ? high-accuracy voltage and current regulation ? buffered reference voltage ? input current regulation accuracy: 5% ? package (100 ma, 500 ma) ? 36-ball, 0.4-mm pitch dsbga package ? charge voltage regulation accuracy: 0.5% (25 c) 2 applications 1% (0 - 125 c) ? mobile phones and smart phones ? charge current regulation accuracy: 5% ? mp3 players ? bad adaptor detection and rejection ? portable navigation devices ? safety limit register for maximum charge voltage and current limiting ? handheld devices ? high-efficiency mini-usb/ac battery charger 3 description for single-cell li-ion and li-polymer battery packs the tps65200 device integrates a high-efficiency, usb-friendly switched-mode charger with otg ? built-in input current sensing and limiting support for single-cell li-ion and li-polymer batteries, ? integrated power fets for up to 1.25-a d+d- detection, a 50-ma fixed-voltage ldo, a high- charge rate efficiency wled boost converter, and high-accuracy ? programmable charge parameters through i 2 c current-shunt monitor into a single chip. interface (up to 400 kbps): the tps65200 comes in a tiny, 2.8-mm 2.6-mm, ? input current 36-pin, 0.4-mm pitch die size ball grid array (dsbga). ? fast-charge/termination current ? charge voltage (3.5 v - 4.44 v) device information (1) ? safety timer part number package body size (nom) ? termination enable tps65200 dsbga (36) 2.60 mm 2.90 mm ? synchronous fixed-frequency pwm (1) for all available packages, see the orderable addendum at controller operating at 3 mhz with 0% to the end of the data sheet. 99.5% duty cycle charging curve ? safety timer with reset control ? reverse leakage protection prevents battery drainage ? thermal regulation and protection ? input/output overvoltage protection ? automatic charging ? boost mode operation for usb otg ? input voltage range (vsys): 2.5 v to 4.5 v ? output voltage for vbus: 5 v ? wled driver ? 35-v open led protection for up to 8 leds ? 200-mv reference voltage with 2% accuracy ? built-in soft start for wled boost 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. 0 100 200 300 400 500 600 700 800 900 1000 0 2000 4000 6000 8000 10000 12000 time [s] c h a r g in g c u rr e n t [m a ] 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 b a tte ry v o l ta g e [v ] charging current battery voltage productfolder sample &buy technical documents tools & software support &community
tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com table of contents 7.4 device functional modes ........................................ 24 1 features .................................................................. 1 7.5 programming ........................................................... 35 2 applications ........................................................... 1 7.6 register maps ......................................................... 36 3 description ............................................................. 1 8 application and implementation ........................ 50 4 revision history ..................................................... 2 8.1 application information ............................................ 50 5 pin configuration and functions ......................... 3 8.2 typical application .................................................. 50 6 specifications ......................................................... 4 9 power supply recommendations ...................... 53 6.1 absolute maximum ratings ...................................... 4 10 layout ................................................................... 53 6.2 esd ratings .............................................................. 5 10.1 layout guidelines ................................................. 53 6.3 recommended operating conditions ....................... 5 10.2 layout example .................................................... 54 6.4 thermal information .................................................. 5 11 device and documentation support ................. 55 6.5 electrical characteristics ........................................... 5 11.1 device support ...................................................... 55 6.6 data transmission timing ...................................... 10 11.2 community resources .......................................... 55 6.7 typical characteristics ............................................ 11 11.3 trademarks ........................................................... 55 7 detailed description ............................................ 18 11.4 electrostatic discharge caution ............................ 55 7.1 overview ................................................................. 18 11.5 glossary ................................................................ 55 7.2 functional block diagram ....................................... 19 12 mechanical, packaging, and orderable 7.3 feature description ................................................. 19 information ........................................................... 55 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (april 2010) to revision a page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .................................................................................................. 1 2 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 5 pin configuration and functions yff package 36-pin dsbga bottom view, top view pin functions pin i/o description no. name a1 bat o output of the linear charger and battery voltage sense. connect the battery from this pin to ground. charge current-sense input. battery current is sensed through the voltage drop across an external sense a2 csout i resistor. a 0.1- f ceramic capacitor to pgnd is required. charge current-sense input. battery current is sensed through the voltage drop across an external sense a3 csin i resistor. a 0.1- f ceramic capacitor to pgnd is required. internal supply for battery charger. connect a 1-mf ceramic capacitor from this output to pgnd. external load a4 vdd o on vdd is not recommended. the voltage on this pin defines the battery voltage for transitioning from linear charge (pre-charge) to fast charge. a 10- a current source is internally connected to this pin. connect a resistor from this pin to ground to a5 vshrt i setup vshort reference. if the pin is left floating or tied to vdd an internal vshort reference of 2.1 v is used. a6 dgnd digital ground b1 b2 pgnd power ground b3 charge status pin. pulled low when charge in progress. open drain for other conditions. this pin can also be b4 stat o controlled through i 2 c register. stat can be used to drive a led or communicate with a host processor. b5 sgnd signal ground b6 vzero i this pin sets the zero-current output voltage level of the current shunt monitor. c1 c2 swc o internal switch to inductor connection (charger) c3 boost control pin. boost mode is turned on whenever this pin is active. polarity is user defined through i 2 c c4 otg i register. the pin is disabled by default and can be enabled through i 2 c register bit. output of current shunt monitor. for positive currents (into battery) vshnt > vzero. for negative currents c5 vshnt o (out of the battery) vshnt < vzero. c6 vsys i input supply for wled driver and current shunt monitor d1 connection point between reverse blocking mosfet and high-side switching mosfet. bypass it with a d2 pmid o minimum of 1- f capacitor from pmid to pgnd. no other circuits are recommended to connect at pmid pin. d3 d4 int o interrupt pin (open-drain). this pin is pulled low to signal to the main processor that a fault has occurred. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: tps65200 ti ymlllls tps65200 ti = ti letters ym = year / month date code llll = lot trace code s = assembly site code o = pin a1 (filled solid) scl otg csin vio vshnt dp swc pmid vshrt stat pgnd pgnd vdd dm boot vbus swc pmid pgnd vbus sda vzero swc bat ldo fb comp pgnd swl vsys pmid int ctrl csout sgnd dgnd dc b a 4 3 2 1 5 e f 6 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com pin functions (continued) pin i/o description no. name control pin of the led boost regulator. it is a multi-functional pin which can be used for enable control and d5 ctrl i pwm dimming. ldo output. ldo is regulated to 4.9 v and drives 60-ma of current. bypass ldo to gnd with at least a 1- f d6 ldo o ceramic capacitor. ldo is enabled when vbus is above the vbus uvlo threshold. e1 charger input voltage. bypass it with a 1- f ceramic capacitor from vbus to pgnd. it also provides power to vbus i/o the load in boost mode. e2 e3 vio i i/o reference voltage. a vio level above 0.6 v disables automatic d+/d- detection. e4 dp i usb port d+ input connection e5 fb i feedback pin for current. connect the sense resistor from fb to gnd. output of the transconductance error amplifier. connect an external capacitor to this pin to compensate the e6 comp o regulator. boot-strapped capacitor for the high-side mosfet gate driver. connect a 10-nf ceramic capacitor (voltage f1 boot o rating above 10 v) from boost pin to swc pin. f2 sda i/o i 2 c interface data f3 scl i i 2 c interface clock f4 dm i usb port d- input connection f5 pgnd power ground this is the switching node of the led driver. connect the inductor from the supply to the swl pin. this pin is f6 swl i also used to sense the output voltage for open led protection. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit supply voltage (with respect to pgnd) vbus ? 2 20 v sda, scl, dm, dp, swl, vzero, vshrt, csin, csout, csot, ldo, int, otg, vsys, vshnt, ? 0.3 7 vdd, vio, bat, ctrl pmid, stat ? 0.3 20 input/output voltage (with respect to v vdd 6.5 pgnd) swc, boot ? 0.7 20 fb,comp ? 0.3 3 swl ? 0.3 44 voltage difference between csin and csout inputs (vcsin -vcsout) 7 v output current (average) swc 1.5 a output current (continuous) ldo 100 ma t a operating ambient temperature ? 40 85 c t j max operating junction temperature 150 c t c max operating case temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. 4 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all 2000 pins (1) v (esd) electrostatic discharge v charged device model (cdm), per jedec specification 500 jesd22-c101, all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit vbus supply voltage 4 6 v swl output voltage vbat 39 v 6.4 thermal information tps65200 thermal metric (1) yff (dsbga) unit 36 pins r ja junction-to-ambient thermal resistance 54.5 c/w r jc(top) junction-to-case (top) thermal resistance 0.2 c/w r jb junction-to-board thermal resistance 8.5 c/w jt junction-to-top characterization parameter 0.9 c/w jb junction-to-board characterization parameter 8.5 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics vbat = 3.6 v 5%, t j = 27 o c (unless otherwise noted) parameter test conditions min typ max unit input currents charger hi-z mode wled disabled 2 10 shunt monitor disabled battery discharge current in high charger hi-z mode impedance mode (csin, 0 c < tj < 85 c, wled enabled, no i discharge a csout,swc, swl, bat, vsys v bat = 4.2 v load 1800 pins) shunt monitor disabled charger hiz mode wled disabled shunt 60 monitor enabled charger pwm on 10000 v bus > v bus(min) i vbus vbus supply current charger pwm off 5000 a 0 c < t j < 85 c, hz_mode = 1 15 leakage current from battery to i vbus_leak 0 c < t j < 85 c, v bat = 4.2 v hiz mode 5 a vbus pin voltage regulation operating in voltage regulation, output charge voltage 3.5 4.44 v programmable v oreg t a = 25 c ? 0.5% 0.5% voltage regulation accuracy full temperature range ? 1% 1% copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com electrical characteristics (continued) vbat = 3.6 v 5%, t j = 27 o c (unless otherwise noted) parameter test conditions min typ max unit current regulation -fast charge v shrt v csout < v oreg v bus > 5 v, r sns = 20 m , 550 1250 low_chg = 0, programmable i ocharge output charge current ma v lowv v csout < v oreg , v bus > 5 v, r sns = 20 m , 150 200 low_chg = 1 charge termination detection v csout > v oreg-vrch , v bus > 5 v, i term termination charge current 50 400 ma r sns = 20 m , programmable both rising and falling, 2-mv overdrive, deglitch time for charge termination 30 ms t rise , t fall = 100 ns charge current accuracy offset voltage, sense voltage amplifier v os, chrgr t a = 0 c to 85 c ? 1 1 mv charge current accuracy = v os /(i set xr sns ) bad adaptor detection input voltage lower limit bad adaptor detection, v bus falling 3.6 3.8 4 v deglitch time for v bus rising above rising voltage, 2-mv over drive, v in(min) 30 ms v in(min) t rise = 100 ns hysteresis for v in(min) v bus rising 100 200 mv i adet current source to gnd during bad adaptor detection 20 30 40 ma t int detection interval input power source detection 2 s input based dynamic power management the threshold when input based charge mode, programmable 4.2 4.76 v dpm loop kicks in v in_low dpm loop kick-in threshold ? 2% 2% tolerance input current limiting i in_limit = 100 ma 88 93 98 i in_limit input current limiting threshold i in_limit = 500 ma 450 475 500 ma i in_limit = 975 ma 875 925 975 vdd regulator v bus > v in(min) or v sys > v batmin , internal bias regulator voltage 2 6.5 v i vdd = 1 ma, c vdd = 1 f v dd vdd output short current limit 30 ma voltage from bst pin to swc pin during charge or boost operation 6.5 v battery recharge threshold recharge threshold voltage below v oreg 100 130 160 mv v rch v csout decreasing below threshold, deglitch time 130 ms t fall = 100 ns, 10-mv overdrive stat output low-level output saturation voltage i o = 10 ma, sink current 0.4 v v ol(stat) high-level leakage current voltage on stat pin is 5 v 1 a reverse protection comparator reverse protection threshold, v bus- v rev 2.3 v v csout v oreg , v bus falling 0 40 100 mv vcsout reverse protection exit hysteresis 2.3 v v csout v oreg 140 200 260 mv v rev-exit deglitch time for v bus rising above rising voltage 30 ms v rev + v rev_exit 6 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 electrical characteristics (continued) vbat = 3.6 v 5%, t j = 27 o c (unless otherwise noted) parameter test conditions min typ max unit vbus uvlo v uvlo ic active threshold voltage v bus rising 3.05 3.3 3.55 v v uvlo_hys ic active hysteresis v bus falling from above v uvlo 120 150 mv pwm f pwm pwm frequency, charger 3 mhz internal top reverse blocking i in_limit = 500 ma, 180 mosfet on-resistance measured from vbus to pmid internal top n-channel switching r dson measured from pmid to swc 120 m mosfet on-resistance internal bottom n-channel measured from sw to pgnd 150 mosfet on-resistance d max maximum duty cycle 99.5% d min minimum duty cycle 0% synchronous mode to low-side mosfet nonsynchronous mode transition 100 ma cycle-by-cycle current sensing current threshold (1) boost mode operation for vbus (opa_mode=1, hz_mode=0) 2.5 v < v bus < 4.5 v; including line and v bus_b boost output voltage (to pin vbus) 4.75 5 5.25 v load regulation over full temp range i bo maximum output current for boost v bus_b = 5 v, 2.5 v < v bus < 4.5 v 200 ma cycle by cycle current limit for i blimit v bus_b = 5 v, 2.5 v < v sys < 4.5 v 1 a boost overvoltage protection threshold for threshold over v bus to turn off converter 5.8 6 6.2 v boost (vbus pin) during boost v busovp vbusovp hysteresis v bus falling from above v busovp 200 mv maximum battery voltage for boost v sys rising edge during boost 4.75 4.9 5.05 v v batmax vbatmax hysteresis v sys falling from above v batmax 200 mv during boosting 2.5 minimum battery voltage for boost v batmin v (vsys pin) before boost starts 2.9 3.05 boost output resistance at high impedance mode (from vbus to hz_mode = 1 500 k pgnd) charger protection threshold over v bus to turn off converter input v busovp threshold voltage 6.3 6.5 6.7 v during charge v ovp-in_usb v ovp_in_usb hysteresis v bus falling from above v ovp_in 140 mv v csout threshold over v oreg to turn off battery ovp threshold voltage 110% 117% 121% charger during charge (% v oreg ) v ovp lower limit for v csout falling from > v ovp v ovp hysteresis 11% (% v oreg ) cycle-by-cycle current limit for i limit charge mode operation 1.8 2.4 3 a charge v csout rising, vshrt connected to vdd 2 2.1 2.2 v trickle to fast charge threshold v bus ? resistor connected from vshrt to gnd 1.8 v 0.7 internal current source connected v short 9.4 10 10.6 a to v shrt pin v short hysteresis v csout falling from above vshort 100 mv enable threshold for internal percentage of vdd 90% v short reference (1) bottom n-channel mosfet always turns on for approximately 60 ns and then turns off if current is too low. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com electrical characteristics (continued) vbat = 3.6 v 5%, t j = 27 o c (unless otherwise noted) parameter test conditions min typ max unit i short trickle charge charging current v csout v short 20 30 40 ma t cf thermal regulation threshold charge current begins to taper down 120 c time constant for the 32-second t 32s 32 second mode 32 s timer wled voltage and current control v ref voltage feedback regulation voltage 198 203 208 mv v fb [4:0] = 01110 (v fb = 25%) 47 50 53 voltage feedback regulation voltage v ref_pwm mv under brightness control v fb [4:0] = 01110 (v fb = 10%) 17 20 23 f ctrl pwm dimming frequency 1 100 khz minimum on-time for pwm dimming t cntrl, min 2.2 s pulse i fb voltage feedback input bias current v fb = 200 mv 1 a f pwm pwm frequency, wled boost 600 khz d max maximum duty cycle v fb = 100 mv 90% 93% t min_on minimum 0n pulse width 40 ns l inductor 10 22 h c out output capacitor 0.47 10 f wled power swiitch r ds(on) n-channel mosfet on-resistance v sys = 3.6 v 300 600 m i ln_nfet n-channel leakage current v swl = 30 v, t a = 25 c 1 a wled protection under voltage lock out (vsys pin) v sys falling 2.2 2.5 v v uvlo uvlo hysteresis 70 mv v ovp overvoltage protection threshold 35 37 39 v i lim n-channel mosfet current limit d = d max 560 700 840 ma i lim_start startup current limit d = d max 400 ma t half_lim time step for half current limit 5 ms t ref v ref filter time constant 180 s t step v ref ramp up time 213 s current shunt monitor v cm common-mode input range v csin = v csout ? 0.3 7 v v csin = 2.7 v to 5 v, v csin ? v csout = 0 cmr common-mode rejection 100 db mv t a = 0 c to 60 c ? 75 75 v os, csm offset-voltage, referred to input v t a = -20 c to 85 c ? 85 85 gain 25 v/v g gain error ? 1% 1% swing to positive power supply rail v sys - v shnt 100 (v sys ) v shnt mv swing to gnd v shnt - v gnd 100 gbw bandwidth c load = 10 pf 9 khz i vzero vzero bias current t a = -20 c to 85 c 10 na swing to positive power supply rail v sys ? v zero 1.5 (v sys ) v zero v swing to gnd v zero - v gnd 0.7 undervoltage lockout (vsys pin) v sys falling 2.2 2.5 v v uvlo uvlo hysteresis 70 mv 8 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 electrical characteristics (continued) vbat = 3.6 v 5%, t j = 27 o c (unless otherwise noted) parameter test conditions min typ max unit ldo ldo output voltage vin = 5.5v 4.8 4.9 5 v v ldo psrr f = 100 hz, cldo = 1.0 f 60 db i ldo maximum ldo output current 60 ma v do dropout voltage vin = 4.5 v, ildo = 50 ma 100 250 mv d+/d- detection d+ voltage source 0.5 0.6 0.7 v v dp_scr d+ voltage source output current 250 a i dm_sink d- current sink 50 100 150 a dm pin, switch open 4.5 5 c i input capacitance pf dp pin, switch open 4.5 5 dm pin, switch open ? 1 1 i i input leakage a dp pin, switch open ? 1 1 v dp_low dp low comparator threshold 0.8 v v dm_high dm high comparator threshold 0.8 v v dm_low dm low comparator threshold 475 mv logic levels and timing charteristics (scl, sda, ctrl, int) output low threshold level i o = 3 ma, sink current (sda, int) 0.4 v ol input low threshold level 0.4 v input high threshold level 1.2 i (bias) input bias current (scl, sda, int) v io = 1.8 v 1 a f scl scl clock frequency 400 khz r ctrl ctrl pulldown resistor 400 800 1600 k t off ctrl pulse width to shutdown ctrl high to low 2.5 ms 7-bit slave address 1101 010 oscillator oscillator frequency 3 mhz f osc frequency accuracy t a = ? 40 c to 85 c ? 10% 10% thermal shutdown thermal trip point 165 t shtdwn c thermal hysteresis 10 copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 6.6 data transmission timing v bat = 3.6 5%, t a = 25 o c, c l = 100 pf (unless otherwise noted) min nom max unit standard mode 100 f (scl) serial clock frequency khz fast mode 400 scl = 100 khz 4.7 bus free time between stop and start t (buf) s condition scl = 400 khz 1.3 scl = 100 khz 50 t (sp) tolerable spike width on bus ns scl = 400 khz scl = 100 khz 4.7 t low scl low time s scl = 400 khz 1.3 scl = 100 khz 4 t high scl high time s scl = 400 khz 0.6 scl = 100 khz 250 t s(dat) sda scl setup time ns scl = 400 khz 100 scl = 100 khz 4.7 t s(sta) start condition setup time s scl = 400 khz 0.6 scl = 100 khz 4 t s(sto) stop condition setup time s scl = 400 khz 0.6 scl = 100 khz 0 3.45 t h(dat) sda scl hold time s scl = 400 khz 0 0.9 scl = 100 khz 4 t h(sta) start condition hold time s scl = 400 khz 0.6 scl = 100 khz 1000 t r(scl) rise time of scl signal ns scl = 400 khz 300 scl = 100 khz 300 t f(scl) fall time of scl signal ns scl = 400 khz 300 scl = 100 khz 1000 t r(sda) rise time of sda signal ns scl = 400 khz 300 scl = 100 khz 300 t f(sda) fall time of sda signal ns scl = 400 khz 300 figure 1. i 2 c data transmission timing 10 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 p s s p t s(dat) t s(sta) t s(sto) t high t h(dat) t h(sta) t low t r( t f t h( sta) t (buf) scl sda tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 6.7 typical characteristics t a = 25 c, unless otherwise specified. 6.7.1 switching charger v bus = 5 v i charge = 150 ma v bus = 5 v i charge = 150 ma figure 2. pwm charge operation figure 3. pwm charge operation 1500 mah li-ion 5.55 whr i charge = 950 ma i in_limit = 975 ma v bus = 5.5 v r in = 60 v bat = 3 v (#165) figure 4. bad adaptor detection figure 5. charging curve i charge = 950 ma i in_limit = 975 ma v short = 2.8 v figure 6. precharge curve figure 7. effective dropout voltage copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: tps65200 0 100 200 300 400 500 600 700 800 900 1000 0 2000 4000 6000 8000 10000 12000 time [s] c h a r g in g c u rr e n t [m a ] 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 b a tte ry v o l ta g e [v ] charging current battery voltage 0 100 200 300 400 500 600 700 0 400 800 1200 1600 2000 charge current [ma] (v b u s -v b a t ) [m v ] 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 time [s] c h a r g i n g c u rr e n t [m a ] 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 b a tte ry v o l ta g e [v ] low_ichg bit set(150ma) charging current battery voltage vshort set to 2.8v tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com switching charger (continued) v bus = 5.5 v figure 8. charger efficiency 6.7.2 otg boost v bat = 3.8 v i load = 200 ma v bat = 3.8 v i load = 200 ma figure 9. start up figure 10. shutdown 12 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 80% 82% 84% 86% 88% 90% 92% 94% 96% 98% 100% 0.4 0.6 0.8 1 1.2 1.4 1.6 charging current[a] e f fici en cy vbat=2.5v vbat=2.8v vbat=3.6v vbat=4.0v tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 otg boost (continued) v bat = 3.8 v i load = 1 ma v bat = 3.8 v i load = 30 ma figure 11. pwm boost operation figure 12. pwm boost operation v bat = 3.8 v i load = 200 ma v bat = 3.8 v i load = 5 ma - 200 ma figure 13. pwm boost operation figure 14. transient response v bat = 3.8 v i load = 200 ma v bat = 3.8 v i load = 200 ma figure 15. i 2 c controlled voltage step figure 16. i 2 c controlled voltage step copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 6.7.3 ldo figure 17. turnon delay figure 18. turnoff delay charger = on at 950 ma v bus = 5.5 v charger = on at 950 ma v bus = 5.5 v figure 19. start-up figure 20. shutdown 50 ma load, charger = on at 950 ma v bus = 5.5 v 50 ma load, charger = on at 950 ma v bus = 5.5 v figure 21. start-up figure 22. shutdown 14 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 ldo (continued) v bus = 5.5 v charger off i load = 5 ma to 50 ma v bus = 5.5 v figure 23. transient response figure 24. otg boost efficiency 6.7.4 wled boost v bat = 3.8 v v fb = 200 mv 7 leds v bat = 3.8 v v fb = 200 mv 7 leds figure 25. start-up figure 26. shutdown copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: tps65200 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 0.05 0.1 0.15 0.2 0.25 0.3 output current [a] e f fici en cy vbat=4.2v vbat=3.6v vbat=2.9v tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com wled boost (continued) v bat = 4.2 v v fb = 200 mv 7 leds v bat = 4.2 v v fb = 20 mv 7 leds figure 27. pwm operation figure 28. pwm operation v bat = 3 v v fb = 200 mv 7 leds v bat = 3 v v fb = 20 mv 7 leds figure 29. pwm operation figure 30. pwm operation 50% duty cycle v bat = 3.8 v v fb = 200 mv v bat = 3.8 v v fb = 200 mv 7 leds (#162) 7 leds figure 31. pwm dimming figure 32. open led protection 16 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 wled boost (continued) v bat = 3.3 v 6 leds figure 33. efficiency figure 34. efficiency v bat = 3.8 v f pwm = 5 khz 7 leds figure 35. wled dimming linearity copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: tps65200 0.001 0.01 0.1 1 0.1 1 10 100 pulse duty cycle [%] v f b [v ] 50% 55% 60% 65% 70% 75% 80% 85% 90% 0 5 10 15 20 wled current [ma] e f fici en cy vbat=2.8v vbat=3.6v vbat=4.2v 50% 55% 60% 65% 70% 75% 80% 85% 90% 0 5 10 15 20 wled current [ma] e f fici en cy 4 leds 10 leds 8 leds 6 leds tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7 detailed description 7.1 overview the tps65200 charger features a synchronous 3-mhz pwm controller with integrated power mosfets, input current sensing and regulation, input-voltage dynamic power management, high-accuracy charge current and voltage regulation, and charge termination. the charger charges the battery in three phases: low-current precharge, constant current fast-charge, and constant voltage trickle-charge. the input current is automatically limited to the value set by the host. the charger can be configured to terminate charge based on user-selectable minimum current level and to automatically restart the charge cycle if the battery voltage falls below the recharge threshold. a safety timer with reset control provides a safety backup for i 2 c interface. the charger automatically enters sleep mode or high impedance mode when the input supply is removed. the charge status is reported to the host using the i 2 c interface and stat pin. the d+d- detection circuit allows automatic detection of a usb wall-charger. if a wall-charger is detected the input current limit is automatically increased from 500 ma to 975 ma. in otg mode the pwm controller boosts the battery voltage to 5 v and provides up to 200-ma of current to the usb output. at very light loads the boost operates in burst mode to optimize efficiency. otg mode can be enabled either through i 2 c interface or gpio control. the tps65200 also provides a wled boost converter with integrated 40-v switch fet, that drives up to 10 wleds in series. the boost converter runs at 600-khz fixed switching frequency to reduce output ripple, improve conversion efficiency, and allows for the use of small external components. the default wled current is set with a sense resistor, and the feedback voltage is regulated to 200 mv, as shown in the typical application. for brightness dimming, the feedback voltage can be changed through the i 2 c interface or by application of a pwm signal to the ctrl pin. in the latter case the feedback voltage is regulated down proportional to the pwm duty cycle (analog dimming) rather than pulsing the led current to avoid audible noise on the output capacitor. for maximum protection, the device features integrated open led protection that disables the tps65200 to prevent the output from exceeding the absolute maximum ratings during open led conditions. a fixed-gain, high-accuracy current shunt monitor senses the voltage drop across an external, 20-m sense resistor and provides an analog output voltage that is proportional to the charge/discharge current of the battery. the sense voltage is amplified by a factor of 25 and offset by v zero , an externally provided reference voltage. v zero is internally buffered to avoid loading of the reference source. 18 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.2 functional block diagram 7.3 feature description 7.3.1 global state diagram during normal operation, tps65200 is either in standby mode or active mode, depending on user inputs. in standby mode, most functions are turned off to conserve power, but the ic can still be accessed through i 2 c bus and the current shunt monitor can be turned on and off. the bias system and main oscillator are turned off in standby mode. the device enters active mode whenever vbus is asserted or the wled driver is turned on. in active mode, the main oscillator and reference system are turned on. the device remains in active mode as long as vbus remains high, the wled driver is enabled or both conditions exist. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: tps65200 wled driver 0.47 m f fb ldo current shunt monitor q 2 q 3 10nf pgnd swc boot pmid r sns 20m w single cell li+ battery csincsout switching charger q 1 vshnt to adc 470k w tsd digital sda bg/bias osc sgnd from uc from /to uc scl dm from usb portfrom usb port dp from usb connector vbus to load d+/d- detection i2c vio vio pgnd from system vzero swl vshrt 1m f vdd r set 10 w stat 220nf comp ctrl from uc system load 10 a int vio 0.6 v vio from usb transceiver otg vio vbat vsys bat dgnd ldo 4.9v, 60ma uvlo m 1m f 1m f 1m f 0.1 f m 0.1 f m 10 f m 10 f m 1 h m 1 f m 10 h m 0.1 f m + tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com feature description (continued) figure 36. global state diagram 7.3.2 led driver operation the tps65200 offers a high-efficiency, high-output voltage boost converter designed for driving up to 10 white led in series. the serial led connection provides even illumination by sourcing the same output current through all leds, eliminating the need for expensive factory calibration. the device integrates 40-v/0.7-a switch fet and operates in pulse width modulation (pwm) with 600-khz fixed switching frequency. for operation, see functional block diagram . the led driver can be enabled either through the ctrl pin or the wled_en bit in the control register. the ctrl input is edge sensitive and should be pulled low at power-up. the ctrl pin allows pwm dimming of the leds whereas the wled_en bit offers simple on/off control only. the wled_en bit has priority over the ctrl pin and when set to 1, the ctrl pin is ignored. if wled_en is set to 0 and the ctrl pin is low for > 2.5 ms, the wled driver is shut down. the feedback loop regulates the fb pin voltage to the reference set by the vfb[4:0] bits in the wled register with a default setting of 200 mv. if any fault occurs during normal operation the driver is disabled, wled_en bit is reset to 0 and the driver is put into fault state until the ctrl pin has been low for > 2.5 ms. the state diagram for the wled driver is shown in figure 37 . 20 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 power down standby active v sys >v uvlo, vsys || v bus >v uvlo, vbus ldo_en = 1 || ch_en_[1:0] != 00 charger not hiz|| wled is on|| charger in hiz mode& wled off wled driver= disabled ldo = off charger= hiz wled driver= on or charger= /hiz startup v bus tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com feature description (continued) 7.3.2.5 current program the fb voltage is regulated to a low 200-mv reference voltage. the led current is programmed externally using a current-sense resistor in series with the led string. the value of the rset is calculated using equation 1 . where ? i led = output current of leds ? v fb = regulated voltage of fb ? r set = current sense resistor (1) the output current tolerance depends on the fb accuracy and the current sensor resistor accuracy. 7.3.2.6 brightness dimming the tps65200 offers two methods of led brightness dimming. when the ctrl pin is constantly high, the fb voltage is regulated to the value set in the wled register which ranges from 0 mv to 200 mv and is divided into 32 steps. for applications requiring higher dimming resolution, a pwm signal can be applied to the ctrl pin to reduce this regulation voltage and dim led brightness. the relationship between the duty cycle and fb voltage is given by equation 2 . where ? duty = duty cycle of the pwm signal ? vfb[4:0] = internal reference voltage, default = 200 mv (2) the ic chops up the internal reference voltage at the duty cycle of the pwm signal and filters it by an internal low pass filter. the output of the filter is connected to the error amplifier as the reference voltage for the fb pin regulation. therefore, although a pwm signal is used for brightness dimming, only the wled dc current is modulated, which is often referred to as analog dimming. this eliminates the audible noise which often occurs when the led current is pulsed in replica of the frequency and duty cycle of pwm control. the regulation voltage itself is independent of the pwm logic voltage level which often has large variations. figure 38. wled analog dimming circuit 7.3.2.7 inductor overcurrent protection the overcurrent limit in the boost converter limits the maximum input current and thus maximum input power for a given input voltage. maximum output power is less than maximum input power due to power conversion losses. therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output. the current limit clamps the peak inductor current and the maximum dc output current equals the current limit minus half of the peak-peak current ripple. the ripple current is a function of switching frequency, inductor value and duty cycle. equation 3 through equation 5 are used to determine the maximum output current. 22 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 d = 1 - v in v out ? idac fb ctrl wled _en vfb [4 :0 ] v = duty cycle vfb fb [4:0] i = led v fb r set ? tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 feature description (continued) where ? d = duty cycle of the boost converter ? v in = input voltage ? v out = output voltage of the boost converter. it is equal to the sum of vfb and the voltage drop across leds. (3) where ? i pp = inductor peak to peak ripple ? l = inductor value ? f s = switching frequency (4) where ? i out(max) = maximum output current of the boost converter ? i lim = overcurrent limit ? = efficiency (5) for instance, for v in = 3 v, 7 leds output equivalent to v out of 23 v, an inductor value of 22 h, a current limit of 700 ma, and an efficiency of 85%, the maximum output current is ~65 ma. 7.3.3 hv ldo tps65200 provides a 4.9-v ldo that is powered off the vbus input. the ldo is enabled whenever v vbus > v uvlo (3.3 v) and disabled when v vbus > v ovp-in_usb (6.5 v). ldo output voltage follows vbus for v vbus < 4.9 v and is regulated to 4.9 v when v vbus > 4.9 v. in any case output current is limited to 100 ma. the ldo can also be disabled by the host by setting the ldo_en bit of the control register to 0. an operational flow chart of the ldo enable is shown in figure 39 . figure 39. state diagram for the hv ldo copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: tps65200 ldo off ldo on ldo_en = 1 ldo_en = 0 power down || = or & = and ( ?) = rising edge ( ?) = falling edge i = out(max) v in ( i - lim i pp 2 h ? v out ) ? i = pp v d in l f s ? tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com feature description (continued) 7.3.4 interrupt pin the interrupt pin is used to signal any fault condition to the host processor. whenever a fault occurs in the ic, the corresponding fault bit is set in the int1, int2, or int3 register, and the open-drain output is pulled low. the int pin is released (returns to hiz state) if any of the int1, int2, int3 registers is accessed by the host, but fault bits are cleared only by reading the intx register containing the bit. however, if a failure persists, the corresponding interrupt bit remains set but no new interrupt is issued. the tsd bit (thermal shutdown) is auto cleared which means that the bit is reset to 0 automatically after the chip has cooled down below the thermal shutdown release threshold. the mask1, mask2, and mask3 registers are used to mask certain events or group of events from generating interrupts. the maskx settings affect the int pin only and have no impact on protection and monitor circuits themselves. 7.3.5 current shunt monitor tps65230 offers an integrated high-precision current shunt monitor to measure battery charging and discharging currents. the inputs of a low-offset amplifier are connected across an external low-value shunt resistor. this shunt voltage is gained up by a factor of 25 and added to a reference voltage connected to the vzero terminal. v shunt > v zero for currents flowing into the battery and v shunt < v zero for currents flowing out of the battery. the reference voltage is buffered by a low-offset, high impedance input buffer. where ? v shunt is the output voltage of the current shunt monitor ? v csin is the charger side of the shunt resistor ? v csout is the battery side of the shunt resistor ? v zero is the 0-current reference voltage ? v offset is the offset of the differential amplifier (6) the offset of the differential amplifier introduces a measurement error of 40 v input referred, equivalent to 2 ma assuming a 20-m shunt resistor which can be calibrated out by the system. the shunt monitor is disabled by default and can be enabled by the host by setting the smon_en bit in the control register to 1. 7.4 device functional modes 7.4.1 charge mode operation for current limited power source, such as a usb host or hub, the high efficiency converter is critical in fully utilizing the input power capacity and quickly charging the battery. due to the high efficiency in a wide range of the input voltage and battery voltage, the switching mode charger is a good choice for high speed charging with less power loss and better thermal management. the tps65200 is a highly-integrated synchronous switched-mode charger with reverse boost function for usb otg support, featuring integrated mosfets and small external components, targeted at extremely space-limited portable applications powered by 1-cell li-ion or li-polymer battery pack. 24 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 v = (v - v ) + v + v shunt csin csout zero offset 25 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 device functional modes (continued) figure 40. state diagram of usb charger circuit the tps65200 has three operation modes: charge mode, boost mode, and high impedance mode. in charge mode, the tps65200 supports a precision li-ion or li-polymer charging system for single-cell applications. in boost mode, tps65200 will boost the battery voltage to vbus for powering attached otg devices. in high impedance mode, the tps65200 charger stops charging or boosting and operates in a mode with very low current from vbus or battery, to effectively reduce the power consumption when the portable device is in standby mode. through carefully designed internal control circuits, tps65200 achieves smooth transition between different operation modes. the global state diagram of the charger is shown in figure 40 and the detailed charging algorithm in figure 41 . hiz mode is the default state of the charger where q1, charger pwm and boost operation is turned off. if any fault occurs during charging, the ch_en[1:0] bits in the control register are reset to 00b (off), fault bits are set in the int2 register, an interrupt is issued on the int pin, and hiz mode is entered. charging is re-initiated by either host control or automatically if vbus is power cycled. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: tps65200 power down hiz adaptor detection charge charge done delay t int boost any charger state otg = active || ch_en[1:0] = 01 ch_en[1:0] = 00 boost fault || ch_en != 01 & otg = not active (ch_en[1:0] = 10 || ch_en[1:0] = 11) & d+/d- detection done term_en = 1 & i term detected & v csout > v oreg -v rch v csout < v oreg -v rch & ch_en[1:0] = 10 v csout > v oreg -v rch v vbus tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 device functional modes (continued) figure 42. adaptor identification algorithm and block diagram 7.4.1.2 bad adaptor detection/rejection (chbadi) at the beginning of the charge cycle, the ic will perform the bad adaptor detection by applying a current sink to vbus. if v vbus is higher than v in(min) for 30 ms, the adaptor is good and the charge process will begin. however, if v vbus drops below v in(min) , a bad adaptor is detected. then, the ic will disable the current sink, issue an interrupt and set the chbadi interrupt in the int2 register. after a delay of tint (2s), the ic will repeat the adaptor detection process, as shown in figure 44 . if the battery voltage is high ( > 3.8 v), it is possible that the input voltage drops below the battery voltage during adaptor rejection test. in this case, the reverse protection will kick-in and disable the charger. also note that the 30-ma current sink is turned on for 30 ms only. if the input capacitance is > 500 f (not recommended), the adaptor may be accepted although it is not capable of providing 30-ma of current. in these cases, the vdppm loop will limit the charging current to maintain the input voltage. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: tps65200 turn on v dp _src , i dm _sink , dp_sw, and dm_sw delay 40ms dpdm_en=0 dp_low = 0 & dm_low = 1 & dm_high = 0 ? no delay 40ms wall charger i limit = 975ma done dpdm_d = 1 yes disabled vio < 0.6v? v bus > v uvlo ,vbus yes turn off v dp _src , i dm _sink , dp_sw, and dm_sw turn off v dp _ src , i dm _sink , dp_sw, and dm_sw no v bus tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 figure 45. precharge to fast-charge transition threshold (vshort) figure 46. typical charging profile of tps65200 without input current limit copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: tps65200 precharge (linear charge) fast charge ( pwm charge) i short termination v short regulation current regulation voltage precharge phase current regulation phase voltage regulation phase charge current charge voltage the input current remains constant during current regulation phase. vshrt 10 m a 90% vdd vdd 1 .05 v r r vbat vbat >vshrt vshort can be adjusted by an external resistor. note that the vshrt pin voltage equals half vshort threshold. when vshrt pin is left floating or is tied to vdd, an internal reference of 1.05 v is used resulting in a 2.1-v pre-charge to fast-charge transition threshold. + + tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com figure 47. typical charging profile of tps65200 with input current limit 7.4.1.6 pwm controller in charge mode the tps65200 provides an integrated, fixed 3-mhz frequency voltage-mode controller with feed-forward function to regulate charge current or voltage. this type of controller is used to help improve line transient response, thereby simplifying the compensation network used for both continuous and discontinuous current conduction operation. the voltage and current loops are internally compensated using a type-iii compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low esr. there is a 0.5-v offset on the bottom of the pwm ramp to allow the device to operate between 0% to 99.5% duty cycles. the tps65200 has two back-to-back common-drain n-channel mosfets at the high side and one n-channel mosfet at the low side. an input n-mosfet (q1) prevents battery discharge when vbus is lower than v csout . the second high-side n-mosfet (q2) behaves as the switching control switch. a charge pump circuit is used to provide gate drive for q1, while a boot strap circuit with external boot-strap capacitor is used to boost up the gate drive voltage for q2. cycle-by-cycle current limit is sensed through the internal sense mosfets for q2 and q3. the threshold for q2 is set to a nominal 1.9-a peak current. the low-side mosfet (q3) also has a current limit that decides if the pwm controller will operate in synchronous or non-synchronous mode. this threshold is set to 100ma and it turns off the low-side n-channel mosfet (q3) before the current reverses, preventing the battery from discharging. synchronous operation is used when the current of the low-side mosfet is greater than 100 ma to minimize power losses. 7.4.1.7 battery charging process during precharge phase, while the battery voltage is below the v short threshold, the tps65200 applies a short- circuit current, i short , to the battery. when the battery voltage is above v short and below v oreg , the charge current ramps up to fast charge current, i ocharge , or a charge current that corresponds to the input current of i in_limit . the slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. both the input current limit (default at 100 ma), i in_limit , and fast charge current, i ocharge , can be set by the host. once the battery voltage is close to the regulation voltage, v oreg , the charge current is tapered down as shown in figure 46 . the voltage regulation feedback occurs by monitoring the battery-pack voltage between the csout and pgnd pins. tps65200 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 v to 4.44 v) programmed through i 2 c interface. 30 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 precharge (linear charge) fast charge (pwm charge) i short termination v short regulation voltage precharge phase current regulation phase voltage regulation phase charge current charge voltage the charging current during current regulation phase decreases as battery voltage increases. this mode ensures fastest charging of the battery without exceeding the adaptor current limit. tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 the tps65200 monitors the charging current during the voltage regulation phase. when the termination threshold, i term , is detected and the battery voltage is above the recharge threshold, the tps65200 terminates charge. the termination current level is programmable and charge termination is disabled by default. to enable the charge current termination, the host can set the charge termination bit term_en of config_c register to 1. refer to i 2 c section for details. a new charge cycle is initiated when one of the following events occur: ? vbus is power-cycled. ? ch_en[1:0] = 11b and the battery voltage drops below the recharge threshold (term_en = 1). ? the reset bit is set (host controlled). ? the device is in charge done state (see figure 40 ) and the term_en bit is set from 1 to 0. 7.4.1.8 thermal regulation and protection during the charging process, to prevent overheating of the chip, tps65200 monitors the junction temperature, t j , of the die and begins to taper down the charge current once t j reaches the thermal regulation threshold, t cf . the charge current will be reduced to zero when the junction temperature increases about 10 c above t cf . at any state, if t j exceeds t shtdwn , tps65200 will suspend charging and enter hiz state. charging will resume after t j falls 10 c below t shtdwn . 7.4.1.9 safety timer in charge and boost mode (ch32mi, bst32si) the tps65200 charger hosts a safety timer that stops any boost or charging action if host control is lost. the timer is started when the ch_en[1:0] bits are set to anything different from 00 and is continuously reset by any valid i 2 c command. if the timer exceeds 32 s and boost mode is enabled (ch_en[1:0] = 01b), the boost is disabled, ch_en[1:0] is set to 00b, boost time-out fault is indicated in the int2 register, and an interrupt is issued. similarly, once the timer exceeds 32 minutes and the charger is enabled (ch_en[1:0] = 10b or 11b), the charger is disabled, ch_en[1:0] is set to 00b, charger time-out fault is indicated in int2 register and an interrupt is issued. time-out faults affect ch_en[1:0] bits only and not charger parameters. the safety timer flow chart is shown in figure 48 . copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 31 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com figure 48. timer flow chart for tps65200 charger 7.4.1.10 input voltage protection in charge mode 7.4.1.10.1 input overvoltage protection (vbusovpi) the tps65200 provides a built-in input overvoltage protection to protect the device and other components against damage if the input voltage (voltage from vbus to pgnd) gets too high. when an input overvoltage condition is detected, the tps65200 turns off the pwm converter, sets the vbusovpi bit in the int1 register and issues an interrupt. once v vbus drops below the input overvoltage exit threshold, the fault is cleared and charge process resumes. 7.4.1.10.2 reverse current protection (chrvpi) the tps65200 charger enters hi-z state if the voltage on vbus pin falls below v csout + v rev , and v bus is still higher than the poor source detection threshold, v in(min) . the chrvpi bit is set in the int2 register and an interrupt is issued. this feature prevents draining the battery during the absence of v bus . in hi-z mode, both the reverse blocking switch q1 and pwm are turned off. 32 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 disable boost ----------------- ch_en[1:0] = 00 bst32si =1 reset and start 32min timer 32s timer expired? ch_en [1:0] = 10? yes yes 32m timer expired? no no ch_en[1:0] != 00 disable charger ----------------- ch_en[1:0] = 00 ch32mi = 1 yes chstat[2:0] = 010? (charge done) no any i2c action? no yes no yes disabled any state ch_en[1:0] = 00 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.4.1.10.3 input voltage based dynamic power management (chdpmi) during normal charging process, if the input power source is not able to support the charging current, v bus voltage will decease. once v vbus drops to v in_low (default 4.36 v), the charge current will taper down to prevent further drop of v bus . this feature makes the ic compatible with adaptors with different current capabilities. whenever the vdpm loop activates, the chdpmi interrupt is set in the int2 register and the int pin is pulled low. the chdpmi interrupt is delayed by 32 ms to prevent the interrupt to occur when the charging source is removed. 7.4.1.11 battery protection in charge mode 7.4.1.11.1 battery charge current limiting whenever a valid power source is connected to the charger, the low_chg bit of the config_c register is set to 1 which limits the charging current to 150 ma. once the host detects that that charging source has been inserted it needs to reset the low_chg bit to 0 to achieve a higher charging current. this feature prevents charging of a battery at high currents when system voltage is too low for the system to boot. 7.4.1.11.2 output overvoltage protection (chbatovpi) the tps65200 provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage gets too high, as when the battery is suddenly removed. when an overvoltage condition is detected, tps65200 turns off the pwm converter, sets the chbatovpi bit in the int2 register, issues an interrupt, and enters hiz mode. once v csout drops to the battery overvoltage exit threshold, charging resumes. 7.4.1.11.3 battery short protection during the normal charging process, if the battery voltage is lower than the short-circuit threshold, v short , the charger will operate in short circuit mode with a lower charge rate of i short . 7.4.1.12 charge status output, stat pin the stat pin is used to indicate charging status of the ic and its behavior can be controlled by setting the stat_en bits of the control register. in auto mode, stat is pulled low during charging and is high- impedance otherwise. stat pin can also be forced low or to hi-z state by setting the stat_en bits accordingly. the stat pin has enough pulldown strength to drive a led and can be used for visual charge status indication. 7.4.2 boost mode operation in 32 second mode, when ch_en[1:0] = 01 in control register, tps65200 operates in boost mode and delivers power to vbus from the battery. in normal boost mode, tps65200 converts the battery voltage (2.5v to 4.5 v) to vbus-b (5 v) and delivers a current as much as ibo (200 ma) to support other usb otg devices connected to the usb connector. boost mode can also be enabled through the otg pin. by default the otg pin is disabled and can be enabled by setting the otg_en bit to 1. the polarity of the otg pin is user programmable through the otg_pl bit. both bits are located in the config_c register. the otg pin allows the usb transceiver to take control of the boost function without involvement of the main processor. 7.4.2.1 pwm controller in boost mode similar to charge mode operation, in boost mode, the tps65200 provides an integrated, fixed 3-mhz frequency voltage-mode controller to regulate output voltage at pmid pin (v pmid ). the voltage control loop is internally compensated using a type-iii compensation scheme that provides enough phase margin for stable operation with a wide load range and battery voltage range. in boost mode, the input n-mosfet (q1) prevents battery discharge when vbus pin is over loaded. cycle-by- cycle current limit is sensed through the internal sense mosfet for q3. the threshold for q3 is set to a nominal 1.0-a peak current. the upper-side mosfet (q2) also has a current limit that decides if the pwm controller will operate in synchronous or non-synchronous mode. this threshold is set to 75 ma and it turns off the high-side n- channel mosfet (q2) before the current reverses, preventing the battery from charging. synchronous operation is used when the current of the high-side mosfet is greater than 75 ma to minimize power losses. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 33 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.4.2.2 boost start up to prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up. 7.4.2.3 pfm mode at light load in boost mode, tps65200 will operate in pulse skipping mode (pfm mode) to reduce the power loss and improve the converter efficiency at light load condition. during boosting, the pwm converter is turned off once the inductor current is less than 75 ma; and the pwm is turned back on only when the voltage at pmid pin drops to about 99.5% of the rated output voltage. a unique pre-set circuit is used to make the smooth transition between pwm and pfm mode. 7.4.2.4 safety timer in boost mode (bst32si) at the beginning of boost operation, the tps65200 starts a 32-second timer that is reset by the host through any valid i 2 c transaction to the ic. once the 32-second timer expires, tps65200 will turn off the boost converter, issue an interrupt, set the bst32si bit in the int3 register, and return to hi-z mode. fault condition is cleared by por or reading the int3 register. 7.4.2.5 protection in boost mode 7.4.2.5.1 output overvoltage protection (bstbusovi) the tps65200 provides a built-in overvoltage protection to protect the device and other components against damage if the vbus voltage gets too high. when an overvoltage condition is detected, tps65200 turns off the pwm converter, resets ch_en[1:0] bits to 00b (off), sets the bstbusovi bit in the int3 register, issues an interrupt, and enters hiz mode. once vvbus drops to the normal level, the boost will start after host sets ch_en[1:0] = 01b. 7.4.2.5.2 output over-load protection (bstoli) the tps65200 provides a built-in over-load protection to prevent the device and battery from damage when vbus is over loaded. once an over load condition is detected, q1 will operate in linear mode to limit the output current while vpmid is kept in voltage regulation. if the over load condition lasts for more than 30 ms, the over- load fault is detected. when an over-load condition is detected, tps65200 turns off the pwm converter, resets ch_en[1:0] bits to 00b (off), sets the bstoli bit in the int3 register, and issues an interrupt. the boost will not start until the host sets ch_en[1:0] = 01b or the otg pin is toggled. 7.4.2.5.3 battery voltage protection (bstlowvi, bstbatovi) during boosting, when battery voltage is above the battery overvoltage threshold, v batmax , or below the minimum battery voltage threshold, v batmin , tps65200 will turn off the pwm converter, reset ch_en[1:0] bits to 00b (off), set the bstlowvi or bstbatovi bit in the int3 register, and issues an interrupt. once the battery voltage goes back to the normal level, the boost will start if the host sets ch_en[1:0] = 01b or the otg pin is toggled. 7.4.3 high impedance mode when ch_en[1:0] bits in the control register are set to 00b, tps65200 will operate in high impedance mode, with the impedance looking into vbus pin higher than 500k . 34 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.5 programming 7.5.1 i 2 c bus operation the tps65200 hosts a slave i 2 c interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to i 2 c standard 3.0. figure 49. subaddress in i 2 c transmission start ? start condition ack ? acknowledge g(3:0) ? group id: address fixed at 1101 s(7:0) ? subaddress: defined per register map a(2:0) ? device address: address fixed at 010 d(7:0) ? data; data to be loaded into the device r/nw ? read / not write select bit stop ? stop condition the i 2 c bus is a communications link between a controller and a series of slave terminals. the link is established using a two-wired bus consisting of a serial clock signal (scl) and a serial data signal (sda). the serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. each device has an open drain output to transmit data on the serial data line. an external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. data transmission is initiated with a start bit from the controller as shown in figure 50 . the start condition is recognized when the sda line transitions from high to low during the high portion of the scl signal. upon reception of a start bit, the device will receive serial data on the sda input and check for valid address and control information. if the appropriate group and address bits are set for the device, then the device will issue an acknowledge pulse and prepare the receive subaddress data. subaddress data is decoded and responded to as per the register map section of this document. data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. a stop condition is recognized as a low to high transition of the sda input during the high portion of the scl signal. all other transitions of the sda line must occur during the low portion of the scl signal. an acknowledge is issued after the reception of valid address, sub-address and data words. the i 2 c interface will auto-sequence through register addresses, so that multiple data words can be sent for a given i 2 c transmission. figure 50. i 2 c start/stop/acknowledge protocol copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 35 product folder links: tps65200 start condition . . . acknowledge stop condition scl sda 1 2 3 4 5 6 7 8 9 . . . g3 g2 a1 a0 r/nw ack start g1 g0 a2 s7 s6 s2 s1 s5 s4 s3 s0 ack d7 d6 d2 d1 d5 d4 d3 d0 ack stop slave address + r/nw sub address data tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6 register maps table 1. register address map address default register name description (hex) value 0 0 control 0000 1010 enable control register 1 1 config_a 0000 0001 charger current register 2 2 config_b 0001 1001 charger voltage register 3 3 config_c 1000 1010 special charger settings 4 4 config_d 0100 0000 charger safety limits settings 5 5 wled 0001 1111 wled feedback voltage setting 6 6 status_a 0100 0000 status register a 7 7 status_b 0000 0001 status register b 8 8 int1 0000 0000 interrupt bits 9 9 int2 0000 0000 interrupt bits (charger) 10 0a int3 0000 0000 interrupt bits (boost) 11 0b mask1 0000 0000 interrupt masking bits 12 0c mask2 0000 0000 interrupt masking bits 13 0d mask3 0000 0000 interrupt masking bits 14 0e chipid 0000 0000 chip id register 36 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.1 control register (control) address ? 0x00h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name stat_en[1:0] smon_en wled_en ldo_en dpdm_en ch_en [1:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 1 0 1 0 field name bit definition stat enable bits 00 ? auto (controlled by charger status) stat_en[1:0 01 ? on (low impedance) 10 ? off (high impedance) 11 ? not defined shunt monitor enable bit smon_en 0 ? disabled 1 ? enabled wled enable bit 0 ? disabled wled_en 1 ? enabled note: wled can also be enabled through ctrl pin. ldo enable bit ldo_en 0 ? disabled 1 ? enabled d+/d- detection enable 0 ? disabled dpdm_en 1 ? enabled note: bit is automatically reset after detection is completed. charger enable bits 00 ? disabled / hiz mode ch_en[1:0] 01 ? boost mode 10 ? charge 11 ? charge with automatic recharge copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 37 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.2 charger config register a (config_a) address ? 0x01h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name lmtsel vichrg[3:0] viterm[2:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 1 field name bit definition (1) input current limit selction lmtsel 0 ? input current limit is set to the higher of iin_limit[1:0] (config_b) and d+d- det. result 1 ? iin_limit[1:0] (config_b) applied, d+d- detection result is ignored charge current sense voltage (current equivalent for 20 m shunt) 0000 ? 11 mv (550 ma) 0001 ? 13 mv (650 ma) 0010 ? 15 mv (75 ma) 0011 ? 17 mv (850 ma) 0100 ? 19 mv (950 ma) 0101 ? 21 mv (105 ma) vichrg[3:0] 0101 ? 21 mv (1050 ma) 0110 ? 23 mv (1150 ma) 0111 ? 25 mv (1250 ma) 1000 ? 27 mv (1350 ma) 1001 ? 29 mv (1450 ma) 1010 ? 31 mv (1550 ma) ... 1111 ? 31 mv (1550 ma) termination current sense voltage (current equivalent for 20 m shunt) 000 ? 1 mv (50 ma) 001 ? 2 mv (100 ma) 010 ? 3 mv (150 ma) viterm[2:0] 011 ? 4 mv (200 ma) 100 ? 5 mv (250 ma) 101 ? 6 mv (300 ma) 110 ? 7 mv (350 ma) 111 ? 8 mv (400 ma) (1) during charging the lower value of vmchrg[3:0] (config_d register) and vichrg[2:0] applies. 38 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.3 charger config register b (config_b) address ? 0x02h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name iin_limit[1:0] voreg[5:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 1 1 0 0 1 field name bit definition (1) input current limit setting 00 ? 100 ma iin_limit[1:0] 01 ? 500 ma 10 ? 975 ma 11 ? no input current limit battery regulation voltage / boost output voltage 00 0000 ? 3.50 v / 4.425 v 00 0001 ? 3.52 v / 4.448 v 00 0011 ? 3.56 v / 4.471 v ... 01 1000 ? 3.98 v / 4.077 v voreg[5:0] 01 1001 ? 4.00 v / 5 v 01 1010 ? 4.02 v / 5.023 v ... 10 1111 ? 4.44 v / 5.5 v ... 11 1111 ? 4.44 v / 5.5 v (1) during charging the lower value of vmreg[3:0] (config_d register) and voreg[5:0] applies. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 39 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.4 charger config register c (config_c) address ? 0x03h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vs_ref otg_pl otg_en term_en low_chg vsreg[2:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 1 0 0 0 1 0 1 0 field name bit definition vshort reference select vs_ref 0 ? internal (2.1 v) reference 1 ? current source on vshrt pin is enabled. pin voltage is used as 0.5 x vshort threshold. otg pin polarity otg_pl 0 ? active low 1 ? active high otg pin enable otg_en 0 ? pin is disabled 1 ? pin is enabled charge termination enable term_en 0 ? disabled 1 ? enabled low charge current enable bit (current equivalent for 20 m shunt) low_chg 0 ? normal charge current sense voltage per register config_a 1 ? 3 mv (150 ma) input voltage dpm regulation voltage 000 ? 4.20 v 001 ? 4.28 v 010 ? 4.36 v vsreg[2:0] 011 ? 4.44 v 100 ? 4.52 v 101 ? 4.60 v 110 ? 4.68 v 111 ? 4.76 v 40 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.5 charger config register d (config_d) address ? 0x04h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vmchrg[3:0] vmreg[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 1 0 0 0 0 0 0 field name bit definition (1) maximum charge current sense voltage (current equivalent for 20 m shunt) 0000 ? 11 mv (550 ma) 0001 ? 13 mv (650 ma) 0010 ? 15 mv (750 ma) 0011 ? 17 mv (850 ma) 0100 ? 19 mv (950 ma) 0101 ? 21 mv (1050 ma) vmchrg[3:0] 0110 ? 23 mv (1150 ma) 0111 ? 25 mv (1250 ma) 1000 ? 27 mv (1350 ma) 1001 ? 29 mv (1450 ma) 1010 ? 31 mv (1550 ma) ? 1111 ? 31 mv (1550 ma) maximum battery regulation voltage 0000 ? 4.20 v 0001 ? 4.22 v 0010 ? 4.24 v vmreg[3:0] ? 1100 ? 4.44 v ... 1111 ? 4.44 v (1) config_d register is reset to its default value when v csout voltage drops below v short threshold (typ.2.05 v). after v csout recovers to v csout > v short config_d register value can be changed by the host until one of the other registers is written to. writing to any other register locks the config_d register from subsequent writes. if config_d is not the first register to be written after reset, the default values apply. during charging the lower value of vmchrg[3:0] and vichrg[2:0] (config_a register), and vmreg[3:0] and voreg[5:0] (config_b register) apply. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 41 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.6 wled control register (wled) address ? 0x05h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used vfb[4:0] read/write r r r r/w r/w r/w r/w r/w reset value 0 0 0 1 1 1 1 1 field name bit definition not used n/a not used n/a not used n/a wled feedback voltage 0 0000 ? 0% 0 0001 ? 2.5% 0 0010 ? 4% 0 0011 ? 5.5% 0 0100 ? 7.5% 0 0101 ? 8.5% 0 0110 ? 10% 0 0111 ? 11.5% 0 1000 ? 13% 0 1001 ? 14.5% 0 1010 ? 16% 0 1011 ? 17.5% 0 1100 ? 19% 0 1101 ? 22% 0 1110 ? 25% vfb[4:0 0 1111 ? 28% 1 0000 ? 31% 1 0001 ? 34% 1 0010 ? 37% 1 0011 ? 40% 1 0100 ? 43% 1 0101 ? 46% 1 0110 ? 49% 1 0111 ? 52% 1 1000 ? 58% 1 1001 ? 64% 1 1010 ? 70% 1 1011 ? 76% 1 1100 ? 82% 1 1101 ? 88% 1 1110 ? 94% 1 1111 ? 100% 42 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.7 status register a (status_a) address ? 0x06h data bit d7 d6 d5 d4 d3 d2 d1 d0 standb field name not used monitor chstat [2:0] ldo wled y read/write r r r r r r r r reset value 0 1 0 0 0 0 0 0 field name bit definition (1) not used n/a standby status indicator standby 0 ? device is in active mode 1 ? device is in standby mode current shunt monitor status indicator monitor 0 ? current shunt monitor is disabled 1 ? current shunt monitor is enabled charger status bit 000 ? high impedance mode 001 ? charge in progress (fast charge) 010 ? charge done chstat [2:0] 011 ? boost mode 100 ? charge in progress (pre charge) 101 ? not defined 110 ? not defined 111 ? not defined ldo status bit ldo 0 ? ldo is disabled (off) 1 ? ldo is enabled (on), no fault wled status bit wled 0 ? wled disabled (off) 1 ? wled enabled (1) default values reflect state after power-on reset, no charger plugged in, no faults present. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 43 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.8 status register b (status_b) address ? 0x07h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name reset not used not used not used not used dpdm_d dpdm_r otg read/write w r r r r r r r reset value 0 0 0 0 0 0 0 1 field name bit definition (1) reset 0 ? no effect reset 1 ? reset all parameters to default values note: read always returns ? 0 ? not used n/a not used n/a not used n/a not used n/a d+/d- detection done bit dpdm_d 0 ? dpdm detection in progress or not started after initial power-up reset 1 ? dpdm detection is complete d+d- detection result dpdm_r 0 ? standard usb port (500-ma current limit) 1 ? usb charger (1000-ma current limit) otg pin status otg 0 ? otg pin at low level 1 ? otg pin at high level (1) default values reflect state after power-on reset, no charger plugged in, no faults present, otg pin high.. 7.6.9 interrupt register 1 (int1) address ? 0x08h data bit d7 d6 d5 d4 d3 d2 d1 d0 not used/ not used/ not used/ not used/ field name tsdi vbusovpi not used wledi reserved reserved reserved reserved read/write r r r r/w r/w r/w r/w r reset value 0 0 0 0 0 0 0 0 field name bit definition thermal shutdown fault. set if die temperature exceeds thermal shutdown threshold. reset when die tsdi temperature drops below tsd release threshold. vbusovpi vbus overvoltage protection. set when v bus > v ovp-in_usb is detected. not used n/a not used / reserved n/a / reserved not used / reserved n/a / reserved not used / reserved n/a / reserved not used / reserved n/a / reserved wledi wled driver over voltage 44 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.10 interrupt register 2 (int2) address ? 0x09h data bit d7 d6 d5 d4 d3 d2 d1 d0 chbatov field name chrvpi chbadi chtermi chrchgi ch32mi chtregi chdpmi i read/write r r r r r r r r reset value 0 0 0 0 0 0 0 0 field name bit definition (1) chrvpi charger fault. reverse protection (vv bus > v in(min) and v vbus < v csout+vrev (fault) chbadi charger fault. bad adaptor (v bus < v in(min) ) chbatovi charger fault. battery ovp chtermi charge terminated chrchgi recharge request (v csout < v oreg ? vrch ) ch32mi charger fault. 32 m time-out (fault) chtregi charger warning. thermal regulation loop active. chdpmi charger warning. input voltage dpm loop active. (1) all charger faults result in disabling the charger (ch_en[1:0] = 00). recharge request disables the charger only if ch_en[1:0] = 10. 7.6.11 interrupt register 3 (int3) address ? 0x0ah data bit d7 d6 d5 d4 d3 d2 d1 d0 bstbuso bstlowv field name bstoli bstbatovi bst32si not used not used not used vi i read/write r r r r r r r r reset value 0 0 0 0 0 0 0 0 field name bit definition (1) bstbusovi boost fault. vbus ovp (v bus > v busovp ) bstoli boost fault. over load. bstlowvi boost fault. battery voltage is too low. bstbatovi boost fault. battery over voltage. bst32si boost fault. 32-s time-out fault. not used n/a not used n/a not used n/a (1) all boost faults result in disabling the boost converter (ch_en[1:0] = 00). copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 45 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.12 interrupt mask register 1 (mask1) address ? 0x0bh data bit d7 d6 d5 d4 d3 d2 d1 d0 vbusov field name tsdm not used not used not used not used not used wledm pm read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 0 field name bit definition (1) tsd fault interrupt mask tsdm 0 ? interrupt not masked 1 ? interrupt masked vbus ovp fault interrupt mask vbusovpm 0 ? interrupt not masked 1 ? interrupt masked not used n/a not used n/a not used n/a not used n/a not used n/a wled fault interrupt mask wledm 0 ? interrupt not masked 1 ? interrupt masked (1) setting any of the interrupt mask bits does not disable protection circuits. when set, the respective fault will not be signaled on the int pin. 46 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.13 interrupt mask register 2 (mask2) address ? 0x0ch data bit d7 d6 d5 d4 d3 d2 d1 d0 chbatov field name chrvpm chbadm chtermm chrchgm ch32mm chtregm chdpmm m read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 0 field name bit definition (1) charger reverse protection interrupt mask chrvpm 0 ? interrupt not masked 1 ? interrupt masked charger bad adaptor interrupt mask chbadm 0 ? interrupt not masked 1 ? interrupt masked charger battery overvoltage interrupt mask chbatovm 0 ? interrupt not masked 1 ? interrupt masked charge terminated interrupt mask chtermm 0 ? interrupt not masked 1 ? interrupt masked charger recharge request interrupt mask chrchgm 0 ? interrupt not masked 1 ? interrupt masked charger 32m timeout interrupt mask ch32mm 0 ? interrupt not masked 1 ? interrupt masked charger thermal regulation loop active interrupt mask chtregm 0 ? interrupt not masked 1 ? interrupt masked charger input current dpm active interrupt mask chdpmm 0 ? interrupt not masked 1 ? interrupt masked (1) setting any of the interrupt mask bits does not disable protection circuits. when set, the respective fault will not be signaled on the int pin copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 47 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 7.6.14 interrupt mask register 3 (mask3) address ? 0x0dh data bit d7 d6 d5 d4 d3 d2 d1 d0 bstbusov bstlowv field name bstolm bstbatovm bst32sm not used not used not used m m read/write r/w r/w r/w r/w r/w r/w r/w r/w reset value 0 0 0 0 0 0 0 0 field name bit definition (1) boost vbus overvoltage interrupt mask bstbusovm 0 ? interrupt not masked 1 ? interrupt masked boost over load interrupt mask bstolm 0 ? interrupt not masked 1 ? interrupt masked boost low battery voltage interrupt mask bstlowvm 0 ? interrupt not masked 1 ? interrupt masked boost battery overvoltage interrupt mask bstbatovm 0 ? interrupt not masked 1 ? interrupt masked boost 32s time out interrupt mask bst32sm 0 ? interrupt not masked 1 ? interrupt masked not used n/a not used n/a not used n/a (1) setting any of the interrupt mask bits does not disable protection circuits. when set, the respective fault will not be signaled on the int pin. 48 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 7.6.15 chip id register (chipid) address ? 0x0eh data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vendor[1:0] chip[2:0] rev[2:0] read/write r r r r r r r r reset value 0 0 0 0 0 0 0 1 (1) (1) device dependent. field name bit definition vendor code 00 ? default vendor[1:0] 00 ? default chip id 000 ? tps65200 chip[2:0] 001 ? future use ... 111 ? future use revision code 000 ? revision 1.0 001 ? revision 1.1 rev[2:0] 010 ? future use ... 111 ? future use copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 49 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps65200 device is designed to serve as a li+ battery charger with an additional wled driver and current shunt monitor. a typical application design for this usage will be described in typical application . 8.2 typical application figure 51. typical application schematic 8.2.1 design requirements the key elements to identify for the design are the value of r set , r shrt , and r sns as well as the desired led brightness. all other values should reflect those required in pin configuration and functions or in functional block diagram . 50 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 c12 pmid gnd gnd c8 vldo 1 f gnd c7 vbus 1 f 1 f d1 d2 d3 d4 int ctrl d5 d6 pmid ldo vbus int ctrl vbus pmid pmid e1 e2 e3 e4 e5 e6 220 nf gnd c6 fb dp vio fb dp vio 10 nf c5 swc boot sda f1 f2 f3 f4 f5 f6 scl dm gnd sda boot comp pgnd dm scl swl swl vlf4010st-100mr80 l1 10 h d1 mbr0540t1 470 nf gnd c1 tps65200 vysy swc vzero swc swc sgnd vshnt otg/ntc pgnd pgnd stat vshrt test pgnd csout csin vdd bat c6 c5 c4 c3 c2 c1 b6 b5 b4 b3 b2 b1 a6 a5 a4 a3 a2 a1 stat vshrt u1 otg/ntc swc nr3012t1r0n l2 1 h 100 nf c3 gnd 100 nf c2 gnd 1 f c4 gnd 10 f c10 gnd 10 f c9 gnd 20 m r5 470 k vsys r7 100 nf c11 gnd vzero gnd gnd vdd tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 typical application (continued) 8.2.2 detailed design procedure to determine the value for r set , simply take the desired i led and divide it by the fb voltage. the fb voltage is 200 mv by default, but can be changed by the vfb[4:0] bits. to determine the value for r shrt , the desired pre-charge to fast-charge voltage threshold must be known. from there, divide the voltage by two to account for an internal divider and then by the reference current for v shrt of 10 ua to determine the resistance value. to determine the value for r sns , determine the desired output voltage for the current being monitored. divide this voltage by the gain, 25 v/v, and the output current to determine the sense resistor value. finally, the led brightness is a function of either changing the feedback voltage through i 2 c or applying a pwm signal to the ctrl pin.[current figure 43 wled dimming linearity] gives some estimate as to the vfb level as a function of the duty cycle of the input pwm. this should be fine-tuned for the particular leds being used. table 2. recommended external components (1) part no. value size manufacturer charger inductor nr3012t1r0n 1 h 3 3 1.2 taiyo yuden cpl2512t1r0m 1 h 2.5 1.5 1.2 tdk mdt2520cn 1 h toko wled boost inductor ell-vgg100m 10 h 3 3 1.5 panasonic vlf4010st-100mr80 10 h 4.3 4 1 tdk 1098as-100m 10 h 3 3.2 1.2 toko wled boost schottky diode mbr0540 sod-123 on-semi zhcs400 sod-323 zetex (1) over operating free-air temperature range (unless otherwise noted). 8.2.3 application curves v bus = 5.5 v v bat = 3.3 v i in_limit = 975 ma v bus = 5.5 v v bat = 3.3 v i in - limit = 975 ma i charge = 950 ma i charge = 950 ma figure 52. i 2 c controlled start-up figure 53. i 2 c controlled start-up copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 51 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 0-a - 1-a transient v bus = 5.5 v v bat = 3.2 v 0-a - 1-a transient v bus = 5.5 v v bat = 3.2 v on v sys on v sys v oreg = 4 v i charge = 950 ma i in_limit = 975 ma v oreg = 4 v i charge = 950 ma i in_limit = 975 ma figure 54. transient response figure 55. transient response 0-a - 1-a transient v bus = 5.5 v v bat = 4 v 0-a - 1-a transient v bus = 5.5 v v bat = 4 v on v sys on v sys v oreg = 4 v i charge = 950 ma i in_limit = 975 ma v oreg = 4 v i charge = 950 ma i in_limit = 975 ma figure 56. transient response figure 57. transient response 0-a - 1-a transient v bus = 5.5 v no battery 0-a - 1-a transient v bus = 5.5 v no battery on v sys on v sys v oreg = 4 v i charge = 950 ma i in_limit = 975 ma v oreg = 4 v i charge = 950 ma i in_limit = 975 ma figure 58. transient response figure 59. transient response 52 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 9 power supply recommendations this device should be connected to a single cell li+ battery or to a 5-v vbus supply. the current required from vbus will depend on the desired limit, maximum of 1.55 a. 10 layout 10.1 layout guidelines as for all switching power supplies, the layout is an important step in the design, especially at high peak currents and switching frequencies. if the layout is not carefully done, the dcdc converters might show noise problems and duty cycle jitter. the input capacitors on vbus and pmid pins should be placed as close as possible to the input pins for good input voltage filtering. the inductors should be placed as close as possible to the switch pins to minimize the noise coupling into other circuits. the output capacitors must be placed directly from the inductor (charger buck) or schottky diode (wled boost) to gnd to minimize the ripple current in these traces. all ground pins must be connected directly to the ground plane as should all passive components with ground connections. figure 60 and figure 61 show one example for placement and routing of the critical components on a four-layer pcb. in this example all components are placed on the top layer and all routing is done on the top layer or bottom layer. layer 2 is a solid ground plane and layer 3 is not used for layout. all ic pin connections are notes as [pin number]. for example, the vsys pin is referenced as [c6]. ? place c9 and c10 (vsys) as close to l2 as possible, with short connections to ground. ? place c4 close to the ic. trace current is low ( < 1 ma). ? place c8 as close to the ic as possible. maximum trace current is 60 ma. ? keep c6 - [e6] trace shielded from swl node to avoid noise coupling. ? place c2 and c3 as close to the ic as possible.connections for c2 - [a3] and c3 - [a2] must not be in any current path; and, must be kept as short as possible. traces must connect directly to sense resistor r5. ? place l1 as close to the ic as possible. keep traces between l1, d1 and [f6] short and wide.maximum trace current is 700 ma. ? pins [a1] and [a2] must not be shorted at the ic. route them separately to r5. ? place c12 (pmid) as close to the ic as possible. ? place input capacitor c7 (vbus) as close to the ic as possible. ? place c1 close to d1 and keep the trace short and wide. ? keep [c1], [c2], [c3] (swc) to l2 connection shortand wide. adding vias is ok. maximum trace current is 2 a. ? keep vsys to l1 connection short and wide. maximum trace current is 700 ma. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 53 product folder links: tps65200 tps65200 slvsa48a ? april 2010 ? revised september 2015 www.ti.com 10.2 layout example figure 60. layout example ? top pcb layer figure 61. layout example ? bottom pcb layer 54 submit documentation feedback copyright ? 2010 ? 2015, texas instruments incorporated product folder links: tps65200 tps65200 www.ti.com slvsa48a ? april 2010 ? revised september 2015 11 device and documentation support 11.1 device support 11.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2010 ? 2015, texas instruments incorporated submit documentation feedback 55 product folder links: tps65200 package option addendum www.ti.com 1-dec-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS65200YFFR active dsbga yff 36 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps65200 tps65200yfft active dsbga yff 36 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 tps65200 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. package option addendum www.ti.com 1-dec-2015 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS65200YFFR dsbga yff 36 3000 180.0 8.4 2.76 3.02 0.83 4.0 8.0 q2 tps65200yfft dsbga yff 36 250 180.0 8.4 2.76 3.02 0.83 4.0 8.0 q2 package materials information www.ti.com 17-jun-2015 pack materials-page 1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS65200YFFR dsbga yff 36 3000 182.0 182.0 20.0 tps65200yfft dsbga yff 36 250 182.0 182.0 20.0 package materials information www.ti.com 17-jun-2015 pack materials-page 2 www.ti.com package outline c 0.625 max 0.30 0.12 2 typ 2 typ 0.4 typ 0.4 typ 36x 0.3 0.2 b e a d 4222008/a 03/2015 dsbga - 0.625 mm max height yff0036 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. bump a1 corner seating plane ball typ 0.05 c a b c d 1 2 3 0.015 c a b e 5 4 f symm symm 6 scale 4.500 www.ti.com example board layout 36x ( )0.23 (0.4) typ (0.4) typ ( ) metal 0.23 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.23 0.05 min 4222008/a 03/2015 dsbga - 0.625 mm max height yff0036 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). solder mask details not to scale symm symm land pattern example scale:25x a b c d 1 2 3 4 5 e f 6 non-solder mask defined (preferred) solder mask defined www.ti.com example stencil design (0.4) typ (0.4) typ 36x ( 0.25) (r ) typ0.05 metal typ 4222008/a 03/2015 dsbga - 0.625 mm max height yff0036 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:30x a b c d 1 2 3 e 4 5 f 6 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2015, texas instruments incorporated |
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